1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of semiconductor devices having reduced silicide strapping of source/drain to body.
2) Description of the Prior Art
It is now well known that strained silicon channels allow higher carrier mobilities, thus improving device performance, and are compatible with mainstream CMOS processing. One emerging technology is the use of SiGe or SiC that is embedded in PFET or NFET devices, respectively, to induce an uniaxial strain in the transistor channel. In a typical process, a recess etch is first performed in the silicon substrate, exposing the STI sidewall. This recess is subsequently filled with epitaxial SiGe or SiC.
The importance of overcoming the various deficiencies is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 6,861,318: Semiconductor transistor having a stressed channel—Semiconductor transistor for integrated circuits, comprises source and drain formed in source and drain recesses, respectively, source and/or drain being made of film material, which is formed to have second lattice having second spacing Inventor: Murthy, Anand.
U.S. Pat. No. 6,531,347: Method of making recessed source drains to reduce fringing capacitance—Manufacture of semiconductor device involves forming source and drain regions that are recessed at prescribed depth below semiconductor substrate surface. Inventor: Huster, Carl.
US20050035409A1: Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit—Inventor: Ko, Chih-Hsin.
U.S. Pat. No. 6,710,413 and US 20020137295A1: Salicide field effect transistors with improved borderless contact structures and a method of fabrication—Salicide FET fabricating method comprises performing thermal annealing on ion-implanted borderless contact openings formed by over-etching deposited dielectric layer. Inventor: Thei, Kong-Beng.
U.S. Pat. No. 6,093,593: Method of forming a gate which provides a reduced corner recess in adjacent shallow trench isolation—Gate formation for semiconductor fabrication has resist protect layer and silicide regions on source and drain. Inventor: Jang, Syun-Ming